Low Power with Improved Noise Margin for Domino Cmos Nand Gate

With the advancement in semiconductor technology, chip density and operating frequency are increasing, so the power consumption in VLSI circuits has become a major problem of consideration. More power consumption increases packaging cost and also reduces the battery life of the devices. So it has become necessity of the VLSI circuits to reduce the dynamic as well as the static power consumption. To reduce leakage power it is necessary to increase the threshold voltage of the circuit. In this paper to reduce the leakage power AVL (Adaptive Voltage Level) circuit technique and Body biasing technique are used. Our paper proposes a technique for reducing power dissipation of CMOS VLSI design while simultaneously improving the noise immunity.